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ADE7518
VAR Absolute Accumulation Mode
The ADE7518 is placed in absolute accumulation mode by
setting the ABSVARM bit in the ACCMODE register (0x0F). In
absolute accumulation mode, the reactive energy accumulation
is done by using the absolute reactive power and ignoring any
occurrence of power below the no load threshold for the active
energy (see Figure 60). The CF pulse also reflects this accumula-
tion method when in absolute accumulation mode. The default
setting for this mode is off. Transitions in the direction of power
flow and no load threshold are active in this mode.
REACTIVE ENERGY
NO LOAD
THRESHOLD
REACTIVE POWER
NO LOAD
THRESHOLD
Figure 60. Reactive Energy Accumulation in Absolute Accumulation Mode
Reactive Energy Pulse Output
The ADE7518 provides all the circuitry with a pulse output
whose frequency is proportional to reactive power (see the
Energy-to-Frequency Conversion section). This pulse fre-
quency output uses the calibrated signal after VARGAIN, and
its behavior is consistent with the setting of the reactive energy
accumulation mode in the ACCMODE register (0x0F). The
pulse output is active low and should preferably be connected to an
LED, as shown in Figure 66.
TO
DIGITAL-TO-FREQUENCY
CONVERTER
VARGAIN[11:0]
Line Cycle Reactive Energy Accumulation Mode
In line cycle reactive energy accumulation mode, the energy
accumulation of the ADE7518 can be synchronized to the
voltage channel zero crossing so that reactive energy can be
accumulated over an integer number of half-line cycles. The
advantage of this mode is similar to that described in the Line
Cycle Active Energy Accumulation Mode section.
In line cycle active energy accumulation mode, the ADE7518
accumulates the reactive power signal in the LVARHR register
for an integral number of line cycles, as shown in Figure 61. The
number of half-line cycles is specified in the LINCYC register.
The ADE7518 can accumulate active power for up to 65,535
half-line cycles.
Because the reactive power is integrated on an integer number
of line cycles, the CYCEND flag in the Interrupt Status 3 SFR
(MIRQSTH, 0xDE) is set at the end of an active energy accumula-
tion line cycle. If the CYCEND enable bit in the Interrupt Enable 3
SFR (MIRQENH, 0xDB) is set, the 8052 core has a pending
ADE interrupt. The ADE interrupt stays active until the CYCEND
status bit is cleared (see the Energy Measurement Interrupts
section). Another calibration cycle starts as soon as the CYCEND
flag is set. If the LVARHR register is not read before a new
CYCEND flag is set, the LVARHR register is overwritten by a
new value.
When a new half-line cycle is written in the LINCYC register,
the LVARHR register is reset, and a new accumulation starts at
the next zero crossing. The number of half-line cycles is then
counted until LINCYC is reached. This implementation provides a
valid measurement at the first CYCEND interrupt after writing
to the LINCYC register. The line reactive energy accumulation
uses the same signal path as the reactive energy accumulation.
The LSB size of these two registers is equivalent.
OUTPUT
FROM
LPF2
%
+
+
48
0
VAROS[15:0]
VARDIV[7:0]
FROM VOLTAGE
CHANNEL ADC
LPF1
ZERO-CROSSING
DETECTION
CALIBRATION
CONTROL
23
LVARHR[23:0]
0
REACTIVE ENERGY
IS ACCUMULATED IN
THE INTERNAL REGISTER,
AND THE LWATTHR
REGISTER IS UPDATED
AT THE END OF THE LINCYC
HALF-LINE CYCLES
LINCYC[15:0]
Figure 61. Line Cycle Reactive Energy Accumulation Mode
Rev. 0 | Page 57 of 128
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